Memory devices include random access memories (RAM) and read only memories (ROM). The categories of RAM and ROM memories further include subclasses of static RAM (SRAM), dynamic RAM (DRAM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable PROM (EEPROM), FLASH memory, and the like. All the foregoing devices employ architecture in the form of an array of bit cells containing plural rows (wordlines) and plural intersection columns (bitlines).
Typically, the address of a memory cell is determined by the intersection of a wordline with a bitline. A particular cell is activated by activating its row through a wordline, which is connected to the control gate of the transistor forming that cell. The cell is then either read or programmed through a bitline.
The trend in semiconductor memory devices is toward higher circuit density with higher numbers of bit cells per device, lower operating voltages, and higher access speeds. To achieve these high densities there have been, and continue to be, efforts toward scaling down device dimensions. As device dimensions shrink, charged stored in memory cells creates undesirable capacitance issues with neighboring elements within the memory device. In particular, current flow in wordlines adjacent to programmed memory cells is often times disturbed resulting in a higher threshold voltage required to activate the row associated with the affected wordline. This phenomenon is referred to as adjacent wordline disturb (AWD). AWD is a particular concern with FLASH memory devices where the non-volatile nature of the device results in charge remaining in programmed cells for long durations of time.